1. Field of the Invention
The invention disclosed broadly relates to the distribution of clock signals in circuits, and more particularly relates to synchronizing the clock signal in Very Large Scale Integration ("VLSI") circuits.
2. Description of the Related Art
Clock signals are usually responsible for coordinating the various operations performed in a circuit. Serious problems can result if the clock signals received by different parts of the circuit are not synchronized. A lack of synchronization can occur because because the different parts of the circuit are at different distances from the clock source. This causes the received clock signals to have different propagation delays and to be out of phase with each other. This problem, known as clock skew, can occur at the system level, the board level, and the chip level, and it becomes more severe as the circuit size increases and as the clock speed increases. At the chip level, trends in VLSI design are exacerbating the problem by moving toward larger chips and higher clock speeds.
Several approaches have been developed to reduce the phase mismatch due to propagation delay. A typical conventional clock distribution network, for example, uses a symmetric H-tree or other symmetric configuration to minimize the clock skew between different locations on a chip. A discussion of such a clock distribution network can be found, for example, in the book Circuits, Interconnections, and Packaging for VLSI, by H. B. Bakuglu.
Another solution for reducing the phase mismatch is to increase the speed at which the clock signals propagate through the circuit, and thus to decrease the propagation delay. To this end, thick, metal wires with reduced capacitance and resistance have been employed. However, the speed of distributing a clock signal is limited by the speed of light in the medium. This, in turn, dictates the minimum time required to propagate through the medium, or the time-of-flight. These limitations limit the potential benefits of this solution.
As an example, assume that the propagation speed of a guided wave in a particular medium is half of the speed of light in a vacuum, or 1.5.times.10.sup.10 cm/sec. Also assume, as is common with modem chips, that the size of the chip is 3 cm. The time required for the wave to propagate 3 cm is 200 ps (a picosecond is 1.times.10.sup.-12 seconds). Further assuming that the chip is to be designed with a skew of no more than 10% of a cycle, then the clock period must be at least 2000 ps, and the clock frequency can be no more than 500 MHZ. In equation form, the frequency is thus equal to speed of light in the medium, multiplied by the allowable skew expressed as a fraction of the period, and divided by the distance traveled: EQU f=speed*(allowable skew fraction)/distance.
It follows then, that for a given chip size and allowable skew, there is an upper limit on the attainable clock frequency because there is an upper limit on the speed with which a wave can propagate through a medium.
A third solution is to use several sub-clocks. The chip may be divided into several regions, and a separate clock can serve each region. This reduces the distance that a clock signal must travel, and allows shorter leads and lower propagation delays. In the example above, providing a different clock for each quadrant of the circuit would reduce the maximum distance by a factor of two. This would allow a maximum clock frequency of 1 GHz. This solution can, theoretically, always allow a higher clock by further subdividing the chip so that the propagation delay is further reduced. In practice, however, this solution creates problems of synchronizing the various clocks. Additionally, each additional clock takes up valuable space on the chip.
Yet another solution is to use a standing wave, such that the phase is substantially the same at all points in the circuit. Two such solutions are described in U.S. Pat. Nos. 5,517,532 and 5,640,112. Both patents require an external clock generator, and also suggest limiting the length of the clock distribution system to either 1/8 or 1/16 of the wavelength of the clock frequency. U.S. Pat. No. 5,640,112 also introduces a phase advancing means, such as an RC circuit with an amplifier, that can be used to synchronize the phase in various branches of the clock distribution system. This offers a solution to the limited length, but at the cost of designing and adding the phase advancing components.
Accordingly, there is a need for a method and apparatus for distributing clock signals which overcome these problems.